1. Field of the Invention
The present invention relates to fabrication of integrated circuit devices, and, more particularly, to a method of forming a semiconductor device with improved electrical characteristics.
2. Description of the Related Art
In the field of semiconductor integrated circuit devices, the dimensions/sizes of various design features are being steadily decreased for a variety of reasons. For example, design feature sizes are being decreased to achieve higher packaging densities for improving device performance, and to improve electrical performance characteristics of the semiconductor devices, such as a field effect transistor.
Complex digital circuits, such as central processing units (CPUs) and the like, demand fast switching transistors. All other things, being equal, the shorter the channel length of a transistor, the faster it will operate. Accordingly, there is a constant drive to reduce the channel-length on modern transistor devices. For example, the longitudinal dimension of a gate electrode of a transistor, i.e., the gate width, may extend to 20 xcexcm, whereas the distance between the drain and source, i.e., the channel length or gate length, may be reduced to 0.2 xcexcm or below.
As the channel length has been reduced to obtain the desired switching characteristic, the length of the gate electrode has also been reduced. Since the gate electrode may only be electrically connected at one end, the electrical charges used to establish a transverse electrical field for forming the channel between the drain region and the source region of the transistor have to be transported along the entire width of the gate electrode. Given the small transverse dimension (length) of the gate electrode, the electrical resistance is relatively high, which may result in higher RC-delay time-constants. Hence, generation of the transverse electrical field used to fully open the channel is delayed, thereby deteriorating the switching time of the transistor. As a consequence, the rise and fall times of the electrical signals are increased and the operating frequency, i.e., the clock frequency, is reduced. Thus, the switching time of the transistor is no longer limited by the drain and source characteristics, but rather, significantly depends on the delay associated with signal propagation along the gate electrode, i.e., the transistor performance depends, at least in part, on the resistance of the gate electrode in the longitudinal direction of the gate electrode, i.e., in the gate width direction.
The manufacturing process of integrated circuits (ICs) involves the fabrication of numerous insulated gate field effect transistors, such as metal oxide semiconductor field effect transistors (MOSFET). There is a constant drive to continually reduce the feature sizes of the transistor structures to increase the integration density and improve device performance with respect to, for example, signal processing time and power consumption. Therefore, there is a demand for ever improved efficient, reliable and relatively inexpensive methods for patterning the structural features and layers in an integrated circuit device that are suitable for use in the mass production of such devices. Optical photolithography is generally used as a standard method for feature definition in such devices in mass production settings. Currently available photolithography steppers using high numerical aperture lenses and deep ultraviolet (UV) exposure light are, for instance, capable of reliably printing feature sizes as small as 0.2 xcexcm.
The formation of the gate electrode is a critical step in the manufacturing process of a field effect transistor (xe2x80x9cFETxe2x80x9d). It is desirable that the gate length dimension, i.e., the lateral extension of the gate electrode between the source and drain electrodes of the FET, be reduced to sizes approaching or even exceeding the resolution limit of the optical imaging systems used for patterning the device features. In a field effect transistor, such as a MOSFET, the gate electrode is used to control an underlying channel formed in the semiconductor substrate between a source region and a drain region. Channel, source region, and drain region are formed in, on, or over a semiconductor substrate which is doped inversely to the drain and source regions. The gate electrode is separated from the channel, the source region and the drain region by a thin insulating gate dielectric layer, generally a layer comprised of silicon dioxide.
During operation, a voltage is supplied to the gate electrode to create an electric field between the gate electrode and the source and drain regions affecting conductivity in the channel region of the substrate beneath the gate conductor. Besides the desired transistor current control function, the gate electrode, the gate dielectric layer, and the regions underlying the gate dielectric layer also act as a capacitor. The amount of this parasitic capacitance depends on the feature size of the gate electrode. In many integrated circuit applications, the transistors are operated in a switching mode with clock frequencies currently as high as 400-600 MHz, and greater clock speeds are envisioned in the future. In this operation mode, the parasitic capacitance has to be continuously charged and discharged, which significantly affects signal performance and power consumption of the device.
An illustrative example of forming a gate electrode according to a typical prior art process will be described with reference to FIGS. 1A-1C. In FIG. 1A, shallow trench isolations 1 arc formed in a substrate 2 to define an electrically active region 30 in which a channel, drain and source regions are to be formed. Subsequently, a thin gate dielectric layer 3 comprised of silicon dioxide is grown by, for example, furnace processing. Then, a polysilicon layer 4A is blanket-deposited, and a photoresist mask 5 is patterned on the polysilicon layer 4A. The patterning of the photoresist mask 5 is typically performed by deep ultraviolet (DUV) photolithography, which is one method used to achieve the smallest feature dimensions of an integrated circuit device without compromising the required throughput. In a subsequent etching step, portions of the polysilicon layer 4A are removed to form a gate electrode 4 (see FIG. 1B).
FIG. 1B is a cross-sectional view of the transistor structure after the photoresist mask 5, portions of the polysilicon layer 4A and the gate dielectric layer 3 have been removed. Subsequently, as shown in FIG. 1C, lightly doped drain (LDD) regions 8 are formed by an ion implantation process with a low dose of dopant material. The implanted dopant ions are diffused by rapid thermal annealing (RTA) so as to partially extend in the area below the gate dielectric layer 3. With reference to FIG. 1C, sidewall spacers 6 are formed adjacent the gate electrode 4 by forming a layer of spacer material, e.g., silicon dioxide, and performing an anisotropic etching process. Next, a further implantation step with a higher dose of dopant atoms is performed to generate the final drain and source regions 7.
In FIG. 1C, a transistor structure fabricated according to conventional methods is shown wherein the drain and source regions 7 are limited by lightly doped drain regions 8, which connect to a channel 9. The transverse dimension of the gate electrode 4 defines a gate length 10. For the sake of clarity, the person skilled in the art will appreciate that the above mentioned processes are merely schematically described. In particular, those skilled in the art will understand that the DUV photolithographical step involves certain sub steps, such as providing an anti-reflecting coating, which are not specifically recited above.
As mentioned above, the gate length 10 is defined by the gate electrode 4, which, in turn, is defined by the DUV photolithographical step and the subsequent etching of the layer from which the gate electrode 4 is formed. This can be problematic if the gate length dimension, i.e., the dimension indicated by the arrow 10, is reduced to less than a size that can be directly and reliably patterned by conventional photolithography techniques. Additionally, etching processes used to form the gate electrode 4 can lead to variations in the gate length of devices fabricated on different substrate wafers, or different locations within a single wafer, or even to variations of the gate length along a gate width direction. This, in turn, may result in strong variations in drive current and accordingly in strong variations in the electrical characteristics and performance of the transistors. Moreover, any lithographic process for achieving such further reduced gate length is very cost-intensive and complex.
Therefore, since the length 10 of the gate electrode 4 significantly influences the electrical characteristics of the transistor, it is important to provide a method of reliably and reproducibly forming gate electrodes to minimize variations in the electrical characteristics of integrated circuits. The formation of gate electrodes in the sub-quarter micron range, to the extent this is possible, conventionally requires especially costly and complex patterning processes using the most up to date patterning tools, such as the previously described deep ultraviolet (DUV) photolithography steppers.
The present invention is directed to a method of making a semiconductor device that solves, or at least reduces, some or all of the aforementioned problems.
The present invention is directed to a method of making a semiconductor device having improved electrical performance characteristics. In one illustrative embodiment, the method comprises forming a masking layer above a semiconducting substrate, forming an opening in the masking layer that is defined by at least two sidewalls, forming sidewall spacers adjacent the sidewalls of the opening that define an exposed surface of the substrate lying between the spacers, and forming a gate dielectric layer on the exposed silicon surface. The method further comprises forming a layer of polysilicon in the opening and above the gate dielectric layer, removing the layer of polysilicon lying outside the opening, forming a layer of refractory metal above the layer of polysilicon in the opening, converting at least some of the layer of refractory metal to a metal silicide, and removing the masking layer.